1. Field of the Invention
The present invention relates to a method for calculating the resistance value inside a semiconductor integrated circuit.
2. Description of the Prior Art
The large scale semiconductor integrated circuit (LSI circuit) has been a key device indispensable for electric and electronic devices. In general, a high speed operable LSI circuit is used in order to improve the performance of electric and electronic devices. However, on the other hand, the high speed operable LSI circuit is a source of high frequency noise.
FIG. 1 shows a model of an internal structure of an LSI circuit. The LSI circuit incorporates resistance R, capacitor C, inductor L, etc., and these components produce electromagnetic interference (EMI). If EMI leaks outside the LSI circuit, a malfunction can be caused in other devices. Thus, it is necessary to provide any countermeasure against the noise that leaks outside the LSI device. However, if the noise check is performed on a completed LSI circuit and noise is detected, the necessity of redesigning the LSI circuit arises, and such a procedure is inefficient.
Noise is produced by each of inductor L, capacitor C and resistance R. If it is possible to estimate EMI produced by these components before designing a LSI circuit, it is possible to efficiently design the LSI circuit. A method for checking EMI produced by capacitor C, inductor L and resistance R before designing a LSI circuit has already been known (see Japanese Unexamined Patent Publication No. 2003-30273).
FIG. 41 illustrates a conventional method for estimating EMI produced by a resistance inside an LSI circuit using a power-supply LPE (Layout Parasitic Extraction) method and a reduction method. As shown in FIG. 41, a power supply line 201 present between external terminal VDD and external terminal VSS (not shown) is extracted from mask layout information. The extracted power supply line 201 is subjected to power-supply LPE method S201, whereby the characteristics of the resistances that constitute the power supply line 201 are determined, and a post layout netlist 202 is obtained. Further, the post layout netlist 202 is subjected to reduction method S202, whereby a large number of resistances are calculated as a single resistance, and the resistance value can be actually calculated.
FIG. 42 illustrates a conventional method for estimating EMI produced by a resistance inside an LSI circuit using a power supply resistance of a primary main power supply line. As shown in FIG. 42, the power supply resistance 213 is calculated by power supply resistance calculation S211 from a main power supply WL 211 which is information about a main-line power supply having a wire width equal to or greater than a predetermined value, and a sheet resistance 212 which has information of the resistance per sheet. Since the primary main line is a simple power supply network, a large number of resistances can be calculated as a single resistance using the LPE method and the reduction method. Further, for the purpose of determining a value with consideration for a wire power supply line, estimation means S212 performs a coefficient multiplication process on the power supply resistance 213 to determine resistance Ri.
However, the conventional methods have the following disadvantages.
In the conventional method which uses the power supply LPE method and the reduction method, an operation is performed such that a large number of resistances present inside the circuit are regarded as a single resistance. However, in a huge system LSI circuit incorporating ten millions of transistors, it is extremely difficult to calculate the resistance of a single transistor even if the reduction method is used because of the limit of the capacity of a computer. Further, an enormous amount of operations are required, and accordingly, the operations take a very long time.
In the conventional method which uses a power supply resistance of a primary main power supply line, only the primary main power supply line is extracted to calculate the resistance. Thus, the resistance value can be calculated even in a complicated circuit including a large number of resistances. However, the resistance of the elements other than the primary main power supply line is not considered in the calculation, and the calculation accuracy of the resistance value is accordingly low.
In view of the above problems, an objective of the present invention is to calculate the resistance value inside a semiconductor integrated circuit with high accuracy within a short time interval as compared with the conventional methods.